Data processing system and microcomputer

ABSTRACT

An input/output device used as a transfer request source outputs a data transfer set command for specifying each transfer channel, each transfer address, the number of transfers, etc. onto a bus together with a data transfer request without being via a CPU. According to the data transfer set command, data transfer control information is set to direct memory access control means, and DMA transfer is started between the input/output device and a memory designated by the transfer address, for example. When the input/output device used as the data transfer request source desires to perform data transfer without noting the state of processing by a microcomputer, it can perform data transfer processing with its timing and the data transfer with the input/output device as a principal base is allowed.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a microcomputer having directmemory access control means incorporated therein, peripheral deviceselectrically connected to the microcomputer, and a data processingsystem using the microcomputer. The present invention also relates to atechnique which is effective for use in a computer system intended toprovide multitask-based high-speed operations.

[0002] There has recently been a demand for improvements in datathroughput in a microcomputer. If the quantity of processed data to beloaded on a CPU (Central Processing Unit) increases, it is difficult toimprove the data throughput of the microcomputer. Therefore, an attempthas been made to incorporate a peripheral module for performing datatransfer control into a microcomputer in place of the CPU to therebydistribute the burden of data processing on the CPU. As such aperipheral module, a DMAC (Direct Memory Access Controller), forexample, is known.

[0003] In the conventional microcomputer having a DMAC incorporatedtherein, the CPU is given the task of initially setting controlinformation (such as transfer addresses, the number of transfers,transfer modes, transfer directions, etc.) necessary for data transferinto the DMAC.

[0004] As an example of such a direct memory access controller referenceis made to a publication entitled “Configuration and Design of Computer(Last Volume)” published by Nikkei BP corporation, pp. 520-521, Apr. 19,1996.

SUMMARY OF THE INVENTION

[0005] However, according to an investigation carried out by the presentinventors, there are cases in which an excessive time is required toinitially set the data transfer control information into the DMAC usingthe CPU, depending on the state of data processing by the CPU or thestate of utilization of an external data bus. It has been proven that,in such a consequence, excessive time has been taken for data transferprocessing. Therefore, there may be cases in which data transfer cannotbe started and ended with the timing required by a data transfer requestsource. There is also a possibility that, since the CPU is used to setthe data transfer control information, the CPU cannot be distributed toother processes during that time, so that the microcomputer will exhibita reduced data processing performance. This becomes one factor whichwill reduce the performance of the entire system.

[0006] An object of this invention is to provide a microcomputer and adata processing system which are capable of setting data transfercontrol information without placing a burden on the CPU, thereby tocarry out a direct memory access with increased system performance.

[0007] Another object of this invention is to provide a microcomputerand a data processing system which are capable of immediately respondingto a request made from a data transfer request source to start datatransfer based on a direct memory access.

[0008] A further object of this invention is to provide a peripheraldevice which is suitable for the issuance of a data transfer request.

[0009] The above and other objects and novel features of the presentinvention will become more apparent from the description provided in thepresent specification and from the accompanying drawings.

[0010] Typical features of the present invention as disclosed in thepresent application will be briefly described as follows.

[0011] That is, when data transfer is carried out, an input/outputdevice (65), used as a transfer request source, outputs a data transferset command (DTR) for specifying a data transfer channel, a datatransfer address, the number of data transfers, a data transfer mode, adata transfer direction, etc. to a bus (60) together with a datatransfer request (TR) without involving the CPU (3). According to thedata transfer set command, data transfer control information is set intothe direct memory access control means (8, 100) and hence data transferplaced under direct memory access control is started between theinput/output device used as the data transfer request source and amemory specified by a transfer address. Thus, when the input/outputdevice used as the data transfer request source desires to perform adata transfer, the input/output device can carry out data transferprocessing at its own timing without regard to the state of processingof the microcomputer (1), whereby data transfer using the input/outputdevice as a principal part or base can be carried out. Since the CPU isnot required to effect the initial setting of the data transfer controlinformation at this time, no load is imposed on the CPU, and the CPU canbe distributed to other processes during that time, thereby contributingto an overall improvement in the data processing performance of themicrocomputer and the data processing performance of the data processingsystem.

[0012] A data processing system comprises a microcomputer (1), a memory(600), an input/output device (65), and at least one bus (60, 61)commonly connected to the microcomputer, the memory and the input/outputdevice. The microcomputer includes a central processing unit (3), directmemory access control means (8, 100) having a plurality of data transferchannels for performing data transfer control based on data transfercontrol information supplied from the central processing unit or theoutside through the bus, and a bus state controller (5) for arbitratingcompetition between bus right requests supplied from the centralprocessing unit, the direct memory access control means and theinput/output device and for controlling a bus cycle for the bus. Theinput/output device acquires a bus right to send a data transfer request(TR) to the direct memory access control means and outputs a datatransfer set command (DTR) for controlling the operation of the directmemory access control means to the bus, and the input/output devicefurther performs the operation of inputting data to or outputting datafrom the bus in synchronism with a response (TDACK) correspondingthereto issued from the microcomputer, operating as a data transfersource for the control of the data transfer by the direct memory accesscontrol means. The direct memory access control means can execute afirst operation (first normal data transfer operation) for performingdata transfer control in accordance with the data transfer controlinformation initially set by the data transfer set command.

[0013] In the first operation as described above, the input/outputdevice, which makes a request for data transfer, can set data transfercontrol information and start data transfer control without involvingthe CPU. Here, the processing of the CPU ranges over various diverseoperations. It has been considered that heretofore in the conventionalmicrocomputer when the CPU is performing another processing at the timedata transfer control information is to be set to the direct memoryaccess control means, the processing of the CPU must be allowed tocontinue until the other process is ended or be interrupted by orthrough the issuing of an interruption or the like, so that an extendedtime is often required to set a data transfer control condition. It isestimated that since the timing for the start and end of data transferis not taken, an influence will be exerted on the performance even uponthe construction of a system. However, in accordance with thisinvention, owing to the direct setting of the data transfer controlinformation by the input/output device without involving the CPU, asdescribed above, the data transfer can be started regardless of thestate of processing of the CPU, whereby the data transfer processingperformance can be improved and the data transfer processing time can beshortened.

[0014] After the first operation, the direct memory access control meansdetects that the data transfer set command (DTR) supplied together withthe data transfer request (TR) from the input/output device has beenplaced in a specific first state (MD1, MD0=“0, 0”), thereby making itpossible to execute a second operation (first handshake protocoltransfer operation) for performing data transfer control according tothe initially set data transfer control information, using the same datatransfer channel as that used for the first operation. A data transferrequest at the time, in which it is unnecessary to change theinitialization condition, can be simply made.

[0015] After the first operation or the second operation, the directmemory access control means is supplied with a data transfer request(TR) from the input/output device without the delivery of the datatransfer set command, thereby making it possible to execute a thirdoperation (second handshake protocol transfer operation) for performingdata transfer control according to the initially set data transfercontrol information, using the same data transfer channel as that usedfor the immediately preceding data transfer operation. Since, in thiscase, the immediately preceding data transfer channel and the datatransfer control information are used for data transfer, theinput/output device can start the data transfer, even if it is not ableto acquire a bus right to set such information.

[0016] Further, the direct memory access control means is supplied withthe data transfer request (TR) from the input/output device with thedata transfer set command (DTR) after the data transfer controlinformation has been initialized by the CPU, thereby making it possibleto execute a fourth operation (second normal data transfer operation)for performing data transfer control according to the data transfercontrol information initialized by the CPU, using a data transferchannel specified by the data transfer set command. The input/outputdevice itself can start up the data transfer even by using the state ofinitialization by the CPU.

[0017] After the data transfer control information has been initiallyset by the CPU, the direct memory access control means is supplied witha data transfer request (TR) from the input/output device without thedelivery of the data transfer set command, thereby making it possible toexecute a fifth operation (third normal data transfer operation) forperforming data transfer control according to the initially set datatransfer control information, using the same data transfer channel asthat used for the immediately preceding data transfer operation. Sincethe previously set data transfer control information is used in thiscase, the input/output device can start data transfer without acquiringa bus right.

[0018] The direct memory access control means detects that a datatransfer set command supplied from the input/output device is placed ina specific second state (ID1, ID0=“0, 0”, MD1, MD0=“0, 0” and SZ2, SZ1,SZ0= “1, 1, 1”), thereby making it possible to force-complete a datatransfer control operation. Thus, when data transfer is required, theinput/output device can stop the data transfer operation of thealready-activated direct memory access control means and request a datatransfer with the highest priority.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] While the specification concludes with claims particularlypointing out and distinctly claiming the subject matter which isregarded as the invention, it is believed that the invention, theobjects and features of the invention and further objects, features andadvantages thereof will be better understood from the followingdescription, when taken in connection with the accompanying drawings, inwhich:

[0020]FIG. 1 is a block diagram showing a data processing systemaccording to one embodiment of the present invention;

[0021]FIG. 2 is a block diagram illustrating a microcomputer accordingto one embodiment of the present invention;

[0022]FIG. 3 is block diagram depicting one example of an external I/O;

[0023]FIG. 4 is a diagram showing a command format illustrative of oneexample of a data transfer set command;

[0024]FIG. 5 is a schematic block diagram illustrating a relationship ofconnections between a DMAC, a DDT, a bus state controller, a memory andan external I/O;

[0025]FIG. 6 is a diagram for describing a first normal data transferoperation with the transfer of data from an external I/O to a memory asan example;

[0026]FIG. 7 is a timing chart concerning the transfer of data from theexternal I/O to the memory under the first normal data transferoperation;

[0027]FIG. 8 is a timing chart concerning the transfer of data from thememory to the external I/O under the first normal data transferoperation;

[0028]FIG. 9 is a diagram for describing a second normal data transferoperation with the transfer of data from an external I/O to a memory asan example;

[0029]FIG. 10 is a timing chart concerning the transfer of data from theexternal I/O to the memory under the second normal data transferoperation;

[0030]FIG. 11 is a timing chart concerning the transfer of data from thememory to the external I/O under the second normal data transferoperation;

[0031]FIG. 12 is a diagram for describing a third normal data transferoperation with the transfer of data from an external I/O to a memory asan example;

[0032]FIG. 13 is a timing chart concerning the transfer of data from theexternal I/O to the memory under the third normal data transferoperation;

[0033]FIG. 14 is a timing chart concerning the transfer of data from thememory to the external I/O under the third normal data transferoperation;

[0034]FIG. 15 is a diagram for describing a first handshake protocoltransfer operation with the transfer of data from an external I/O to amemory;

[0035]FIG. 16 is a timing chart concerning the transfer of data from theexternal I/O to the memory under the first handshake protocol transferoperation;

[0036]FIG. 17 is a timing chart concerning the transfer of data from thememory to the external I/O under the first handshake protocol transferoperation;

[0037]FIG. 18 is a diagram for describing a second handshake protocoltransfer operation with the transfer of data from an external I/O to amemory as an example;

[0038]FIG. 19 is a timing chart concerning the transfer of data from theexternal I/O to the memory under the second handshake protocol transferoperation;

[0039]FIG. 20 is a timing chart concerning the transfer of data from thememory to the external I/O under the second handshake protocol transferoperation;

[0040]FIG. 21 is a diagram for describing a direct data transferoperation with the transfer of data from an external I/O to a memory asan example;

[0041]FIG. 22 is a timing chart concerning the transfer of data from theexternal I/O to the memory under the direct data transfer operation;

[0042]FIG. 23 is a timing chart concerning the transfer of data from thememory to the external I/O under the direct data transfer operation;

[0043]FIG. 24 is a diagram for describing a data transfer interruptoperation;

[0044]FIG. 25 is a timing chart showing a data transfer interruptoperation; and

[0045]FIG. 26 is a diagram illustrating connections between a DDT and aDMAC.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] In order to facilitate an understanding of the present invention,a description will first be made here of the outline of operationsperformed by an external input/output device (external I/O) when a datatransfer request origin or source principally sets data transfer controlinformation into a DMAC and requests the DMAC to perform data transfer,in relation to a microcomputer and an overall data processing system.Afterwards, their functions (data transfer setting functions based onthe external I/O) will be described in detail.

[0047] Microcomputer

[0048]FIG. 2 shows a microcomputer according to one embodiment of thepresent invention. Although the invention is not restricted inparticular, the microcomputer 1 shown in the drawing is constructed ofintegrated circuits on a single semiconductor substrate, likemonocrystalline silicon. The microcomputer 1 has a floating point unit(also called “FPU”) 2. Further, the microcomputer 1 is provided with acentral processing unit (also called “CPU”) 3 capable of operating onintegers. Although the invention is not limited in particular, themicrocomputer 1 has a 32-bit RISC (Reduced Instruction Set Computer)architecture provided with a 16-bit fixed length instruction set.

[0049] Designated by numeral 4 in FIG. 2 is an address translation/cacheunit. The address translation/cache unit 4 has an instruction addresstranslation buffer (also called “instruction TLB”) 40 for instructionsand a separately provided data unified address translation buffer (alsocalled “unified TLB”) 41; so that an instruction access and a dataaccess can be executed by the CPU 3 in parallel. Further, an instructioncache memory 42 and a data cache memory 43 are individually provided. Acache/address translation buffer controller (also called “cache TLBcontroller”) 44 controls the address translation/cache unit 4 as awhole.

[0050] Designated by numeral 5 in FIG. 2 is a bus state controller (buscontroller), which is electrically connected to the addresstranslation/cache unit 4 through a pair of 32-bit data buses 50 and a29-bit address bus 51. A DMAC 8 is electrically connected to the busstate controller 5 through a pair of 32-bit data buses 54 and an addressbus 55.

[0051] The setting of data transfer control information into the DMAC 8can be performed either by the CPU 3 or from the outside of themicrocomputer 1 through a DDT 100. The DDT 100 is a bridge circuit forsupplying the data transfer control information or the like suppliedfrom the outside of the microcomputer 1 to the DMAC 8.

[0052] In the microcomputer 1, the CPU 3 and the DMAC 8 constitute a busmaster module. An external access of the microcomputer 1 is performed byan external bus interface circuit 6 electrically connected to the busstate controller 5 through a 64-bit data bus 52 and an address bus 53.The external bus interface circuit 6 is electrically connected to anexternal data bus 60 and an external address bus 61. Further, the busstate controller 5 outputs strobe signals RAS, CAS and a write enablesignal WE or the like to an externally-provided memory.

[0053] The microcomputer 1 has a clock pulse generator (also called“CPG”) 70, an interrupt control circuit 71, a serial communicationinterface controller (SCI1, SCI2) 72, a real-time clock circuit 73 and atimer 74 as built-in peripheral circuits electrically connected to a16-bit peripheral data bus 56 and a peripheral address bus 57. Theseperipheral circuits may be accessed by the CPU 3 or by DMAC 8 throughthe bus state controller 5. Further, a clock signal CLK synchronizedwith a system clock is outputted from the clock pulse generator 70. Themicrocomputer 1 takes in or captures data from the outside, for example,in synchronism with the system clock signal CLK.

[0054] The bus state controller 5 makes a decision as to an access datasize, an access time and a wait state according to the circuit to beaccessed (corresponding to an address area to be accessed) by the CPU 3or by the DMAC 8 and controls bus accesses to the peripheral buses 56and 57 and the external buses 60 and 61. Further, the bus statecontroller 5 arbitrates competition between bus use requests issued fromthe cache TLB controller 44, the DMAC 8 and the outside. A data buffer58 included in the bus state controller 5 temporarily latches transferdata to accommodate the difference between operation velocities ofcircuits connected to the internal buses 50 and 51, the peripheral buses56 and 57 and the external buses 60 and 61. Further, the DMAC 8transfers data from the data buffer 58 to a transfer destination withoutcapturing the data latched in the data buffer 58 under the data transfercontrol of the DMAC 8. Thus, the transfer of data is performed so as toavoid the needless transfer of data between the DMAC 8 and the databuffer 58.

[0055] The CPU 3 outputs an instruction address to a 32-bit instructionaddress bus 30 when it fetches instructions, and fetches instructionsoutputted to the instruction data bus 31. Further, the CPU 3 outputs adata address to a 32-bit data address bus 32, and reads (loads) datathrough a 32-bit data bus 33 and writes (stores) data through a 32-bitdata bus 34. The instruction address and the data address are bothlogical addresses.

[0056] Although the invention is not restricted in particular, the FPU 2is not provided with a memory addressing capability for accessing thedata cache memory 43 or the like. The CPU 3 performs all addressingoperations for accessing data in place of the FPU 2. In this way, theneed for the provision of a memory address circuit in the FPU 2 iseliminated so as to economize on the chip area. The loading of data intothe FPU 2 is performed through the 32-bit data bus 33 and a 32-bit databus 35, whereas the storing of data from the FPU 2 is carried outthrough a 64-bit data bus 36. The transfer of data from the FPU 2 to theCPU 3 is performed using the low-order 32 bits of the 64-bit data bus36.

[0057] The CPU 3 fetches not only data for the FPU 2. but also all theinstructions, including floating point instructions for the FPU 2. Afloating point instruction fetched by the CPU 3 is supplied from the CPU3 to the FPU 2 via the 32-bit data bus 34.

[0058] Although the invention is not limited in particular, themicrocomputer 1 handles a virtual address space defined by a 32-bitvirtual address and a physical address space defined by a 29-bitphysical address. Address translation information for converting avirtual address to a physical address includes a virtual page number anda physical page number corresponding thereto. An address translationtable is formed in an unillustrated external memory of the microcomputer1. of address translation information in the address translation tableprovided within the external memory not shown in the drawing, themost-recently-used address translation information is stored in theinstruction TLB 40 and the unified TLB 41. The required control isperformed by an operating system of the microcomputer 1, for example.

[0059] The unified TLB 41 for the data stores therein addresstranslation information about data and instructions in the form of 64entries at a maximum. The unified TLB 41 associatively retrieves aphysical page number corresponding to a virtual page number of a virtualaddress outputted to the data address bus 32 by the CPU 3 for purposesof a data fetch from the address translation information and translatesthe virtual address to a physical address.

[0060] The instruction TLB 40 for the instructions stores thereininstruction-dedicated address translation information in the form of 4entries at a maximum. In particular, the entries held by the instructionTLB 40 are defined as some of the address translation informationrelating to instruction addresses held by the unified TLB 41. That is,when it is found from the associative retrieval that no intended addresstranslation information exists in the instruction TLB 40, this addresstranslation information is supplied from the unified TLB 41 to theinstruction TLB 40. The instruction TLB 40 associatively retrieves aphysical page number corresponding to a virtual page number of a virtualaddress outputted to the instruction address bus 30 by the CPU 3 forpurposes of an instruction fetch from address translation information.When the intended address translation information exists (TLB hit), thecorresponding virtual address is converted to a physical address usingthe intended address translation information. When no intended addresstranslation information exists therein (TLB miss), the cache TLBcontroller 44 controls the operation for obtaining the intended addresstranslation information from the unified TLB 41.

[0061] The data cache memory 43 receives the physical address convertedby the unified TLB 41 for a data fetch and performs cache-entryassociative retrieval based on the physical address. If the result ofretrieval is found to be a read hit, then data corresponding to thephysical address is outputted to the data bus 33 or 35 through a cacheline related to the hit. If the result of retrieval is found to be aread miss, then data corresponding to one cache line including datarelated to its miss is read from the unillustrated external memorythrough the bus controller 5 to perform a cachefill operation. Thus, thedata related to the cache miss is read onto the bus 33 or 35. If theresult of retrieval is found to be a write hit, then data is writteninto a hit entry if a cache operation mode is a copyback mode and adirty bit for the corresponding entry is set. The state of mismatchingwith the data of the external memory is found from the dirty bit placedin the set state. When the corresponding dirty cache entry is expelledfrom the cache memory by the cachefill operation, data is written backto the external memory. In a write-through mode, data is written intothe hit entry and the writing of data to the external memory is alsoperformed together. If the result of retrieval is found to be a writemiss, then a cachefill operation is performed in the case of thecopyback mode, and a dirty bit is set to update a tag address, afterwhich data is written into a cache line subjected to the cachefilloperation. In the case of the write-through mode, data is written intothe external memory alone.

[0062] The instruction cache memory 42 receives the physical addressconverted by the instruction TLB 40 for an instruction fetch andassociatively retrieves a cache entry, based on the physical address. Ifthe result of retrieval is found to be a read hit, then an instructioncorresponding to the physical address is outputted to the instructiondata bus 31 from a cache line related to the hit. If the result ofretrieval is found to be a read miss, then data corresponding to onecache line including an instruction related to the miss is read from theunillustrated external memory through the bus controller 5, whereby acachefill operation is performed. Thus, the instruction related to themiss is supplied to the CPU 3 through the instruction data bus 31.

[0063] The instruction TLB 40, the unified TLB 41 and the cache TLBcontroller 44 constitute a memory management unit. The memory managementunit can set the right to have access to a virtual address space andperform memory protection in a privileged mode and a user mode. Forexample, address translation information has protection key data foreach virtual address page number. The protection key data is 2-bit dataobtained by representing page access rights in the form of codes. Any ofthe access rights capable of reading in the privileged mode, reading andwriting in the privileged mode, reading in both the privileged and usermodes, and reading and writing in both the privileged and user modes canbe set. When an actual access type infringes on the access rights set bythe protection key data, a TLB protection infringement exception isgenerated. When the TLB protection infringement exception occurs, theprotection infringement is solved by an exception process and thereaftera return instruction from the exception process is executed tore-execute the interrupted normal process instruction.

[0064] Data Processing System

[0065]FIG. 1 shows one example of a data processing system together withthe details of the DMAC 8. In FIG. 1, the peripheral data bus 56 and theperipheral address bus 57 are indicated generically as “peripheralbuses”, the address buses 50 and the data bus 51 are indicatedgenerically as “internal buses”, and the external data bus 60 and theexternal address bus 61 are indicated generically as “external buses”.Further, the circuits designated at numerals 70 through 74 areidentified generically as built-in peripheral modules (built-inperipheral circuits).

[0066] Although the invention is not limited in particular, an externalROM (Read Only Memory) 62 in which programs, constant data, etc. arestored, an external RAM (Random Access Memory) 63 used as a main memoryor the like, a memory mapped I/O (Input/Output) 64, and an externalinput/output device 65 (corresponding to an external I/O withacknowledgment) having a storage area which eliminates the need forspecifying or designating each address from the outside, as in the caseof an FIFO (First In First Out) buffer or the like, are typicallycoupled to the external buses 60 and 61 as external peripheral circuits.The external I/O 65 is a device for performing the operation ofinputting or outputting data as a data transfer request origin or sourcein a single addressing mode of the DMAC 8. The external I/O 65 serves asa semiconductor device, such as a communication I/O, a protocol controlI/O or the like. The external I/O 65 has the function of acquiring a busright and outputting a data transfer set command to the external bus 60and initially sets data transfer control information to the DMAC 8through the DDT 100. Further, the external I/O 65 has the function ofrequesting the DMAC 8 to transfer data.

[0067] The DMAC 8 has four data transfer channels (data transferchannels 0 to 3) comprising n=0, 1, 2 and 3, for example, and includes asource address register unit 90 including source address registers SARnto which transfer source addresses are set for each of the data transferchannels, a destination address register unit 91 including destinationaddress registers DARN to which transfer destination addresses are setfor each of the data transfer channels, a transfer count register unit92 including transfer count registers TCRn for counting the number oftimes that data is transferred for each of the data transfer channels,and a channel control register unit CHCRn to which a data transfercontrol state or the like is set for each of the data transfer channels.A data transfer channel is a functional unit for handling the transferof data between storage devices, the transfer of data between a storagedevice and peripheral circuits or the transfer of data betweenperipheral circuits. An operation register DMAOR common to therespective data transfer channels is further provided.

[0068] The respective registers SARn, DARn, TCRn, CHCRn and DMAOR arecommonly connected to a bus 80. The bus 80 is electrically connected toa bus interface circuit 81. The bus interface circuit 81 is electricallyconnected to the internal bus 51 through the data bus 54 and it is alsoconnected to the bus state controller 5 through the address bus 55.While the data bus 54 is shown as being electrically connected to theinternal bus 51 to facilitate illustration in the drawing, the data bus54 actually is electrically connected to the internal bus 51 through thebus state controller 5, as described previously with reference to FIG.2.

[0069] The data bus 54 is used for a read/write operation for allowingthe CPU 3 to initially set data transfer control information into theregisters SARn, DARn, TCRn, CHCRn and DMAOR and to confirm the contentsof its setting. The read/write operation is performed by the CPU 3through the address translation/cache unit 4. A signal for selectingeach register referred to above is supplied via the internal bus 51 andthe data bus 54.

[0070] The setting of the data transfer control information into theregisters SARn, DARn, TCRn and CHCRn also may be performed from theoutside of the microcomputer 1 through the DDT 100. In the exampleillustrated in FIG. 1, the main element used for its setting correspondsto the external I/O 65. The external I/O 65 allows the bus controller 5to assert a bus use request signal DBREQ, so that a bus use approvalsignal BAVL is asserted from the bus controller 5, thereby obtaining abus right. Thereafter, the external I/O 65 outputs a data transfer setcommand DTR to the external bus 60. The data transfer set command DTR issupplied to the DDT 100 so that information included in the datatransfer set command DTR is supplied to the registers SARn, DARn, TCRnand CHCRn through a DDT control circuit and a DDT buffer as datatransfer control information.

[0071] The address bus 55 is used to allow the DMAC 8 to supply anaccess address signal to the built-in peripheral circuits and theexternal peripheral circuits through the bus state controller 5 during adata transfer operation. The bus interface circuit 81 suppliesinstructions for a read or write operation, under the data transfercontrol of the DMAC 8, to the bus state controller 5. The bus statecontroller 5 determines the potential of the write enable signal WE inaccordance with the instructions issued from the bus interface circuit81.

[0072] The DMAC 8 has a number-of-times control circuit 82, a registercontrol circuit 83, start-up control circuit 84 and a request prioritycontrol circuit 85 as control circuits used for data transfer controlusing the data transfer channels. When data transfer requests are madefrom the inside and outside of the microcomputer 1, the request prioritycontrol circuit 85 refers to channel enable bits or the like of thechannel control registers CHCRN to determine, in response to the datatransfer requests, whether a data transfer channel to be started up oractivated is capable of operation. Further, when data transfer requestscompete with each other, the request priority control circuit 85determines one data transfer channel to be started up, in accordancewith a predetermined precedence. When the request priority controlcircuit 85 has determined one data transfer channel to respond to thecorresponding data transfer request, it supplies information on the datatransfer channel to the start-up control circuit 84. The start-upcontrol circuit 84 first issues to the bus state controller 5 a busright request signal BREQ so as to demand a bus right. When a bus rightacknowledgment signal BACK is asserted by the bus state controller 5,the DMAC 8 acquires a bus right. Further, the start-up control circuit84 allows the register control circuit 83 to control output operationsor the like of the source registers SARn and destination registers DARnand causes the bus interface circuit 81 to control an address outputoperation or the like. Thus, the DMAC 8 performs data transfer controlresponsive to the data transfer requests through the bus statecontroller 5. The bus state controller 5 starts up a bus cycle on thebasis of the number of memory cycles corresponding to the address areafor the address signal supplied from the DMAC 8.

[0073] Although the invention is not restricted in particular, the datatransfer requests made from the built-in peripheral circuits of themicrocomputer 1 are given by an input capture interrupt signal TICoutputted from the timer (TMU) 74, a transmit data empty interrupttransfer request signal SCI1E outputted from a serial communicationinterface controller SCIL, a receive data full interrupt transferrequest signal SCI1F outputted from the serial communication interfacecontroller SCIL, a transmit data empty interrupt transfer request signalSCI2E outputted from a serial communication interface controller SCI2,and a receive data full interrupt transfer request signal SCI2Foutputted from the serial communication interface controller SCI2.

[0074] The data transfer requests (external requests) made to the DMAC 8from the outside of the microcomputer 1 are first given by transferrequest signals DREQ0 and DREQ1. Although the invention is not limitedin particular, the external requests are made effective or valid by datatransfer channels 0 and 1 alone. When the transfer requests based on thetransfer request signals DREQ0 and DREQ1 are accepted, transferacknowledgment signals DRAK0 and DRAK1 are sent back to each transferrequest source. The completion of data transfer operations responsive tothe transfer request signals DREQ0 and DREQ1 is sent back to thetransfer request sources in accordance with transfer completion signalsDACK0 and DACK1.

[0075] The external I/O 65 can secondly make the external requeststhrough a transfer request signal TR and a data transfer control setcommand DTR. The transfer request signal TR is supplied to the DDT 100through a dedicated signal line 101. A data transfer channel to bestarted up at this time is determined according to the contents of thesignal and data transfer set command DTR outputted from the external I/O65 together with the transfer request signal TR, and control thereof isperformed by a DDT control circuit 102. Reference numeral 200 in the DDTcontrol circuit 102 indicates a buffer for holding a data transfer setcommand DTR. The buffer holds the previously-supplied data transfer setcommand DTR therein until the next new data transfer set command DTR issupplied thereto. Reference numeral 201 indicates a decoder for decodinga specific bit of the data transfer set command DTR held in the buffer200. The specific bit is a bit indicative of a data transfer channel inthe data transfer set command DTR, for example. Since the data transferset command DTR is held in the buffer 200, a data transfer channel to bestarted up can be determined by referring to the data transfer setcommand DTR held in the buffer 200 when a third normal data transferoperation to be described subsequently by reference to FIGS. 12 through14 is specified. For example, the decoder 201 can determine a datatransfer channel to be started up upon the third normal data transferoperation by decoding a bit (corresponding to a bit for designating adata transfer channel) in the data transfer set command DTR held in thebuffer 200. Without providing the buffer 200, a DDT buffer 103 may beused in place of the buffer 200. That is, since a data transfer setcommand DTR is held in the DDT buffer 103 as will be described laterusing FIG. 5, the DDT buffer 103 may be utilized in place of the buffer200.

[0076] Data Transfer Setting Function by External I/O

[0077]FIG. 3 shows one example of the external I/O 65. Although theinvention is not restricted in particular, the external I/O 65 has anFIFO data buffer 120, a command output buffer 121, a controller 122, acommand ROM 123, and a processor 124. The processor 124 has functions,such as a communication control function, an image processing function,a voice processing function, etc., which are not subject to anyrestrictions. The input of data from the bus 60 to the processor 124 andthe output of data from the processor 124 to the bus 60 are performedvia the FIFO data buffer 120. The controller 122 controls the externalI/O 65 as a whole. The command ROM 123 holds a data transfer set commandDTR therein in advance. The controller 122 obtains access to the commandROM 123 to internally transfer a predetermined data transfer set commandDTR to the command buffer 121, so that the data transfer set command DTRof the command buffer 121 is outputted to the external data bus 60 witha timing designated or specified by the controller 122.

[0078] The controller 122 outputs a bus use request signal DBREQ and atransfer request signal TR, both shown typically, and inputs a bus useapproval signal BAVL, a data strobe signal TDACK and a channelidentification signal ID therein. The signals DBREQ, TR, BAVL and TDACKare set as low enable signals. Incidentally, other interface signalscorresponding to other functions of the processor 124 are omitted fromthe drawing.

[0079] Under the data transfer control of the DMAC 8, the external I/O65 serves as a device set as a data transfer source or destination in asingle addressing mode without performing addressing based on an addresssignal. The data strobe signal TDACK is regarded as a signal fordesignating or specifying a timing provided to perform the operation ofinputting or outputting data to or from the external I/O 65 in thesingle addressing mode by-the DMAC 8. It is needless to say that theexternal I/O 65, which serves as the data transfer request source forthe DMAC 8, recognizes whether the external I/O 65 performs either adata input operation or a data output operation. The channelidentification signal ID is a signal which permits the identification ofa data transfer channel through which the DMAC 8 is performing datatransfer control.

[0080]FIG. 4 shows one example of the data transfer set command DTR.Although the invention is not restricted in particular, the datatransfer set command is set to 64 bits and has command formats whichrespectively hold transfer size data SZ2 through SZ0, read/write data(data indicative of read or write) RW, data transfer request channeldata ID1 and ID0, data transfer request mode data MD1 and MD0, datatransfer number-of-times data CT7 through CT0, and data transferaddresses A31 through A0. Although the invention is not limited inparticular, the data transfer set command is 64 bits in the presentembodiment and is set to be the same as the bus size of the externaldata bus 60. Therefore, the command can be supplied from the externalI/O to the microcomputer with one data transfer, and the data transferoperation can be speeded up. Of course, the data transfer set commandDTR is divided into parts, which may be sequentially supplied to themicrocomputer on a time basis.

[0081] In the transfer size data SZ2 through SZ0, “000” means a byte (8bits), “001” means a word (16 bits), “010” means a long word (32 bits),“011” means a quad word (64 bits), “100” means 32 bytes, and “111” means“absence” respectively. Other bits are set as undefined. In theread/write bit RW, “0” means read from a memory and “1” means write tothe memory.

[0082] The data transfer request channel bits ID1 and ID0 identify datatransfer requests with respect to a data transfer channel 0 at “00”, adata transfer channel 1 at “01”, a data transfer channel 2 at “10”, anda data transfer channel 3 at “11”.

[0083] The MD1 and MD0 are bits used to designate a transfer operationmode for the DMAC 8. “00” means a handshake protocol using a data bus,“01” means edge sense, “10” means level sense, and “11” means cyclesteal respectively. Incidentally, the operation mode required of theDMAC 8 by the external I/O 65 will not be determined by the datatransfer set command alone. As will be apparent from the subsequentdescription, the operation mode is determined in relation even to thestates of signals such as the transfer request signal TR, etc.

[0084]FIG. 5 shows in detail the relationship between the DMAC 8, theDDT 100, the bus state controller 5, the external ROM 62 and the RAM 63referred to generically as a memory 600, and the external I/O 65employed in the data processing system illustrated in FIG. 1. The buses52 and 53 and external bus interface circuit 6 provided inside themicrocomputer 1 are omitted from the drawing to facilitate theunderstanding of the drawing. Although the DDT 100 and the buscontroller 5 are illustrated as if they directly interface with theexternal buses 60 and 61, it is to be understood that the relationshipprovided by the connections shown in FIG. 1 is actually maintained.

[0085] The operation register DMAOR of the DMAC 8 has a control bit DDTMinitially set by the CPU 3. The control bit DDTM indicates whether thedata transfer control is to be provided by the DDT 100, in other words,whether the principal setting or the like of data transfer controlinformation from the external I/O 65 should be allowed. The value of thecontrol bit DDTM is supplied to the bus controller 5 and the DDT 100through a control signal ddtmode. Thus, when the data transfer controlusing the DDT 100 is allowed, the DDT 100 is made operable and the buscontroller 5 is able to output a bus use approval signal BAVL and a datastrobe signal TDACK in response to a bus use request based on a signalDBREQ. When the bus use approval signal BAVL is asserted, the buscontroller 5 allows the DDT 100 to assert a signal bavl. Thus, the DDT100 can recognize that the external I/O 65 has acquired a bus right.

[0086] The DDT buffer 103 in the DDT 100 inputs and holds a datatransfer set command DTR therein. The DDT controller 102 controls thesetting of data transfer control information to the DMAC 8 and thestart-up of a DMA transfer operation in accordance with the contents ofthe supplied data transfer set command DTR, the state of a transferrequest signal TR, etc. When it is necessary to set the data transfercontrol information to the registers SARn, DARn and CHCRn, data transferchannels designated by the data transfer request channel data ID1 andID0 included in the data transfer set command DTR are specified andpieces of information about the commands in command formats are suppliedto the corresponding registers SARn, DARn and CHCRn in accordance withthe command formats. A request for the start-up of the data transferoperation is performed using request signals DDTREQ0 through DDTREQ3 forevery one of the data transfer channels.

[0087] Upon carrying out the data transfer control, the DMAC 8 outputs asignal id for indicating a data transfer channel to be activated, and astrobe signal tdack for indicating the start of data transfer to a datatransfer source in a single addressing mode. The signals id and tdackare set as control signals ID and TDACK through the bus controller 5 andare supplied to the external I/O 65.

[0088] While the setting of the data transfer control information to therespective registers has been described using FIG. 5, etc., anadditional description will be made using FIG. 26 to facilitate furtherunderstanding of the invention.

[0089] In FIG. 26, the same elements as those shown in FIG. 5 areidentified by the same symbols. Data transfer request channel data ID1and ID0 in a data transfer set command DTR supplied from a bus 60 aredecoded by a decoder 300. A source address register SAR to which atransfer source address is set, a destination address register DAR towhich a transfer destination address is set, a transfer count registerTCR for counting the number of times that transfer is performed, and achannel control register CHCR to which the state of data transfercontrol for each data transfer channel is set, are defined for each ofthe data transfer channels (corresponding to data transfer channels 0through 3). Therefore, the decoder 300 decodes the data transfer requestchannel data ID1 and ID0 to detect the data transfer channels to be set,whereby the corresponding registers (SAR, DAR, TCR and CHCR) can bedefined from respective register groups (SARn, DARn, TCRn and CHCRn).That is, a DDT control circuit 102 detects data transfer channels inaccordance with the result of decoding by the decoder 300 and selects(designates) respective registers corresponding to the detected datatransfer channels from the register groups (SARn, DARn, TCRn and CHCRn).Respective data held in a DDT buffer 103 are supplied and set to theselected registers through selectors 302, 303, 304 and 305,respectively. For example, address data A0 through A31 in the datatransfer set command DTR are supplied and set to the source addressregister SAR or the destination address register DAR through theselector 302 or 303. Further, data transfer number-of-times data CT7through CT0 in the data transfer set command DTR are supplied and set tothe transfer count register TCR through the selector 304. Moreover, dataMD1 and MD0 in the data transfer set command DTR, for designatingtransfer operation modes, and size data SZ2, SZ1, SZ0, etc. in the datatransfer set command DTR are supplied and set to the channel controlregister CHCR through the selector 305.

[0090] On the other hand, the selection and setting of the respectiveregisters by the CPU 3 are performed as follows: Since an address spaceof the CPU 3 is mapped to each register, address signals supplied to aninternal address bus 51 from the CPU 3 through an address translationunit 4 are decoded by a decoder 301 so that registers to be set areselected from the respective register groups (SARn, DARn, TCRn andCHCRn). Further, respective set data outputted to a data bus 50 from theCPU 3 are respectively supplied and set to the selected registersthrough the selectors 302, 303, 304 and 305.

[0091] Whether the respective selectors 301, 302, 303 and 304 supplydata outputted from a DDT 100 to the register groups or supply data onthe internal bus 50 to the register groups, is determined according tothe value of the control bit DDTM. Although the invention is not limitedin particular, the control bit DDTM is initially set to a value suchthat the internal bus 50 is connected to the above-described registerswhen the power for the microcomputer is turned on.

[0092] Incidentally, the bus 80 and the bus interface circuit 81 havebeen omitted to facilitate the description of FIG. 26. It is to beunderstood that these elements are provided between the selectors andthe internal bus 50 in FIG. 26. It is also to be understood that theregister control circuit 83 is provided with the decoder 301.

[0093] A description will next be made of data transfer protocols at thetime that the external I/O 65 is used as a data transfer request source.Although the invention is not restricted in particular, the datatransfer protocols include a first normal data transfer operation, asecond normal data transfer operation, a third normal data transferoperation, a first handshake protocol transfer operation, a secondhandshake protocol transfer operation, a direct data transfer operationand a data transfer interrupt operation.

[0094] Although the invention is not restricted in particular, the DDT(Demand Data Transfer) control circuit 102 makes a decision as towhether any of the data transfer protocols is designated.

[0095] As will be understood from the subsequent description, the firstnormal data transfer operation is performed using control information(such as a transfer source address or a transfer destination address,etc.) designated by a data transfer set command, and data transferchannels. The second normal data transfer operation is carried out byusing control information designated by the CPU and data transferchannels designated by a data transfer set command. Further, the thirdnormal data transfer operation is performed by using the controlinformation and data transfer channels that were used in the immediatelypreceding transfer operation.

[0096] The first handshake protocol transfer operation is started basedon a specific data transfer set command (information on a bus) and atransfer request signal, whereas the second handshake protocol transferoperation is started based on a transfer request signal (indicative ofthe absence of the information on the bus).

[0097]FIG. 6 is a diagram for describing the first normal data transferoperation in which the transfer of data from an external I/O to a memoryis shown as an example. The form of representation shown in FIG. 6corresponds to that in FIG. 5. In FIG. 6, a DMA register 800 is ageneral representation of the registers SARn, DARn, TCRn, CHCRn andDMAOR. A DMA controller 801 is a general representation of the start-upcontrol circuit 84 and the request priority control circuit 85. FIG. 7shows a timing chart concerning the transfer of data from the externalI/O to the memory during the first normal data transfer operation. FIG.8 illustrates a timing chart concerning the transfer of data from theexternal I/O to the memory during the first normal data transferoperation.

[0098] The first normal data transfer operation is carried out asfollows: An external I/O 65 obtains a bus right, and thereby outputs atransfer set command DTR to the bus 60 and supplies a transfer requestsignal TR to the DDT 100 through the dedicated signal line 101. Thus,the DDT 100 initially sets data transfer control information to the DMAregister 800 in accordance with the contents of the transfer set commandDTR and instructs the DMA controller 801 to start data transfer. Inresponse to this, the DMAC 8 performs a data transfer control operationin a single addressing mode, and hence the external I/O 65 outputs datato a transfer destination as a data transfer request source or inputsdata from a transfer source memory 600.

[0099] Described more specifically, when it is desired to start DMAtransfer, the external I/O 65 first requests the bus controller 5 togive it a bus right, based on a bus right request signal DBREQ. A bususe approval signal BAVL is asserted so that the external I/O 65acquires the bus right. The external I/O 65 asserts a transfer requestsignal TR after two cycles of a clock signal CLK (corresponding to anoperation reference clock signal of a system) since the assertion of thebus use approval signal BAVL, and outputs a data transfer set commandDTR to the external data bus 60. The DDT 100 recognizes the supply ofthe transfer request signal TR with the data transfer set command DTR inresponse to a signal bavl asserted in synchronism with the assertion ofthe signal BAVL. The data transfer set command DTR is supplied to both aDDT buffer 103 and a DDT controller 102. Although the invention is notrestricted in particular, the first normal data transfer operation ismade possible for a data transfer channel 0 alone. The DDT controller102 makes a decision as to whether data ID1 and ID0 in the data transferset command DTR indicate a transfer request to the data transfer channel0. If the answer is found to be Yes, then the DDT controller 102initially sets data transfer control information to the DMA register 800related to the data transfer channel 0 in accordance with the contentsof the data transfer set command DTR and brings it to a state capable ofstarting data transfer according to a start-up request to a datatransfer operation for the data transfer channel 0. After the completionof its initial setting, the DDT controller 102 instructs the DMAcontroller 801 to start the data transfer operation for the datatransfer channel 0 in response to a request signal DDTREQ0. Thus, theDMAC 8 starts the data transfer control in the single addressing mode inaccordance with the initial setting. That is, a data strobe signal TDACKis outputted together with each address signal. In synchronism withthis, the external I/O 65 performs a data output operation from a timeti shown in FIG. 7 as the data transfer request source or performs adata input operation from a time tj shown in FIG. 8. When the externalI/O 65 is set as a data transfer source as shown in FIGS. 6 and 7,channel identification information ID outputted from the bus controller5 is not required. However, when the external I/O 65 is set as a datatransfer destination, it captures data from the memory 600 only when thechannel identification information ID is “00”, which refers to the datatransfer channel 0, as shown in FIG. 8. In FIGS. 7 and 8, a DRAM(Dynamic Random Access Memory) or a synchronous. DRAM is used as thememory 600, RA indicates a row address, CA indicates a column address,BA indicates the selection of a memory bank in which respective strobesignals RAS, CAS and WE are made valid, WT indicates that the operationdesignated by the strobe signal WE at this time is a write operation,and RD indicates that the operation is a read operation. Further, dataD0, D1, D2, D3 and the like are outputted or inputted in synchronismwith the clock signal CLK.

[0100] If the external I/O 65 used as the data transfer request sourcedesires to perform data transfer in accordance with the first normaldata transfer operation, it can carry out data transfer processing withits timing without noting the state of processing by the microcomputer1, whereby the data transfer with the external I/O 65 as a principalpart or base is allowed. Since the CPU 3 is not required for the initialsetting of the data transfer control information, no load is imposed tothe CPU 3 and the CPU 3 can be distributed to other processes duringthat time, whereby the data processing performance of the microcomputer1 and the data processing performance of the data processing system as awhole can be improved.

[0101]FIG. 9 is a diagram for describing a second normal data transferoperation in which the transfer of data from an external I/O to a memoryis shown as an illustrative example. FIG. 10 shows a timing chartconcerning the transfer of data from the external I/O to the memoryduring the second normal data transfer operation. FIG. 11 shows a timingchart concerning the transfer of data from the memory to the externalI/O during the second normal data transfer operation.

[0102] The second normal data transfer operation is carried out asfollows: A CPU 3 performs the initial setting of data transfer controlinformation to a DMA register 800. Thereafter, the data transfer requestTR is supplied from the external I/O 65 together with the data transferset command DTR, whereby data transfer control based on the datatransfer control information initially set by the CPU 3 is performedusing data transfer channels specified by the data transfer set command.Although the invention is not restricted in particular, the secondnormal data transfer operation is valid for data transfer channels 1through 3.

[0103] Described more specifically, when it is desired to start DMAtransfer after the DMA register 800 has been initialized by the CPU 3,the external I/O 65 first requests a bus controller 5 to issue a busright through the use of a bus right request signal DBREQ. A bus useapproval signal BAVL is asserted so that the external I/O 65 acquiresthe bus right. The external I/O 65 asserts a transfer request signal TRafter two cycles of a clock signal CLK (corresponding to an operationreference clock signal of a system) since the assertion of the bus useapproval signal BAVL, and outputs a data transfer set command DTR to anexternal data bus 60. The DDT 100 recognizes that the transfer requestsignal TR is supplied with the data transfer set command DTR in responseto a signal bavl asserted in synchronism with the assertion of thesignal BAVL. The data transfer set command DTR is supplied to both theDDT buffer 103 and the DDT controller 102. Although the invention is notrestricted in particular, the second normal data transfer operation ismade possible for data transfer channels 1 through 3 alone. The DDTcontroller 102 makes a decision as to whether data ID1 and ID0 (ID) inthe data transfer set command DTR indicate a transfer request to any ofthe data transfer channels 1 through 3. If the answer is found to beYes, then the DDT controller 102 does not change the setting of the DMAregister 800 in accordance with the contents of the data transfer setcommand DTR and instructs a DMA controller 801 to start a data transferoperation in response to one of request signals DDTREQ1 through DDTREQ3corresponding to the data transfer channels designated by the data ID1and ID0. Thus, the DMAC 8 starts the data transfer control in a singleaddressing mode in accordance with the data transfer control informationalready initially set by the CPU 3. As a result, a data strobe signalTDACK is outputted together with each address signal from the buscontroller 5. In synchronism with this, the external I/O 65 performs adata output operation from a time ti shown in FIG. 10 or performs a datainput operation from a time tj shown in FIG. 11 as the data transferrequest source. The utilization of the channel identificationinformation ID outputted from the bus controller 5 is the same as thecase shown in FIG. 8.

[0104] According to the second normal data transfer operation, theexternal I/O 65 itself can start the data transfer even using the stateinitially set by the CPU 3.

[0105]FIG. 12 is a diagram for describing a third normal data transferoperation in which the transfer of data from an external I/O to a memoryis shown by way of example. FIG. 13 shows a timing chart concerning thetransfer of data from the external I/O to the memory during the thirdnormal data transfer operation. FIG. 14 illustrates a timing chartconcerning the transfer of data from the memory to the external I/Oduring the third normal data transfer operation.

[0106] The third normal data transfer operation is carried out asfollows: After the CPU 3 has initially set data transfer controlinformation to a DMA register 800 or after the second normal datatransfer operation, a data transfer request signal TR is supplied fromthe external I/O 65 without being accompanied by the data transfer setcommand DTR, whereby new data transfer control according to theinitially-set data transfer control information is performed by usingthe same data transfer channel as that of the immediately preceding datatransfer operation. Although the invention is not restricted inparticular, the third normal data transfer operation is effective fordata transfer channels 1 through 3.

[0107] Described more specifically, when it is desired to start DMAtransfer after the DMA register 800 has been initially set by the CPU 3or after the second normal data transfer operation, the external I/O 65asserts a transfer request signal TR without making a bus right request.At this time, a data transfer set command DTR is not outputted to anexternal data bus 60. When the DDT 100 has recognized a state in whichthe transfer request signal TR is asserted without the assertion of asignal bavl, the DDT controller 102 instructs the DMA controller 801 tostart a data transfer operation according to one of request signalsDDTREQ1 through DDTREQ3 so as to use the same data transfer channel asthat used in the immediately preceding data transfer operation. Thus, aDMAC 8 starts data transfer control in a single addressing mode inaccordance with the conditions already initially set by the CPU 3. As aresult, a bus controller 5 outputs a data strobe signal TDACK togetherwith each address signal. In synchronism with this, the external I/O 65performs a data output operation from a time ti shown in FIG. 13 orcarries out a data input operation from a time tj shown in FIG. 14 as adata transfer request source. The utilization of channel identificationinformation ID outputted from the bus controller 5 is the same as thecase shown in FIG. 8.

[0108] According to the third normal data transfer operation, theexternal I/O 65 can start the data transfer without obtaining the busright after the data transfer control information has been set by theCPU 3.

[0109]FIG. 15 is a diagram for describing a first handshake protocoltransfer operation in which the transfer of data from an external I/O toa memory is shown by way of example. FIG. 16 shows a timing chartconcerning the transfer of data from the external I/O to the memoryduring the first handshake protocol transfer operation. FIG. 17illustrates a timing chart concerning the transfer of data from thememory to the external I/O during the first handshake protocol transferoperation.

[0110] The first handshake protocol transfer operation is an operationfor performing DMA transfer continuously after the first normal datatransfer operation. On condition that a data transfer set commandsupplied together with a data transfer request TR from the external I/O65, after the first normal data transfer operation has been performedinitially, is placed in a specific first state, e.g., MD1, MD0=“0, 0”,data transfer control according to the data transfer control informationinitially set upon the initial first normal data transfer operation isperformed using the same data transfer channel as that used for theinitial first normal data transfer operation.

[0111] Described more specifically, when it is desired to start DMAtransfer after a data transfer channel 0 has been used to designate MD1,MD0=“1, 0” or “1, 1” and the first normal data transfer operation hasbeen performed in this state, the external I/O 65 first requests a buscontroller 5 to issue a bus right through the use of a bus right requestsignal DBREQ. A bus use approval signal BAVL is asserted so that theexternal I/O 65 acquires the bus right. The external I/O 65 asserts atransfer request signal TR after two cycles of a clock signal CLK(corresponding to an operation reference clock signal of a system) sincethe assertion of the bus use approval signal BAVL, and outputs a datatransfer set command DTR to an external data bus 60 as MD1, MD0=“0, 0”.A DDT 100 recognizes that the transfer request signal TR is suppliedwith the data transfer set command DTR in response to a signal bavlasserted in synchronism with the assertion of the signal BAVL. A DDTcontroller 102 detects MD1, MD0=“0, 0” to thereby recognize thedesignation of the first handshake protocol transfer operation andrequests a DMA controller 801 to start data transfer according to atransfer request signal DDTREQ0 without re-setting the data transfercontrol information based on the data transfer set command DTR. Thus, aDMAC 8 starts the data transfer using the data transfer controlinformation already set to the data transfer channel 0 as it is. As aresult, a data strobe signal TDACK is outputted together with eachaddress signal. In synchronism with this, the external I/O 65 performs adata output operation from a time ti shown in FIG. 16 or performs a datainput operation from a time ti shown in FIG. 17 as a data transferrequest source. The utilization of the channel identificationinformation ID outputted from the bus controller 5 is the same as thatof the case shown in FIG. 8.

[0112] According to the first handshake protocol transfer operation, thedata transfer request issued from the external I/O 65 can be easilyperformed where it is unnecessary to change the data transfer controlconditions initially set by the command for the first normal datatransfer operation.

[0113]FIG. 18 is a diagram for describing a second handshake protocoltransfer operation in which the transfer of data from an external I/O toa memory is shown by way of example. FIG. 19 shows a timing chartconcerning the transfer of data from the external I/O to the memoryduring the second handshake protocol transfer operation. FIG. 20illustrates a timing chart concerning the transfer of data from thememory to the external I/O during the second handshake protocol transferoperation.

[0114] The second handshake protocol transfer operation is an operationfor performing DMA transfer continuously after the first normal datatransfer operation. On condition that a data transfer request TR isissued in a state in which an external I/O 65 has no acquisition of abus right, data transfer control according to the data transfer controlinformation initially set upon the initial first normal data transferoperation is performed using the same data transfer channel as that usedfor the initial first normal data transfer operation.

[0115] Described more specifically, when the external I/O 65 desires tostart DMA transfer after a data transfer channel 0 has been used todesignate MD1, MD0=“1, 0” or “1, 1” and the first normal data transferoperation has been performed in this state, the external I/O 65 outputsa data transfer request TR to a DDT controller 102. At this time, theDDT controller 102 confirms, based on a signal bavl, a state in whichthe external I/O 65 has no acquisition of a bus right. As a result, theDDT controller 102 recognizes the designation of the second handshakeprotocol transfer operation and requests a DMA controller 801 to startdata transfer in accordance with a transfer request signal DDTREQ0.Thus, a DMAC 8 starts the data transfer using the data transfer controlinformation already set to the data transfer channel 0 as it is. As aresult, a data strobe signal TDACK is outputted together with eachaddress signal. In synchronism with this, the external I/O 65 performs adata output operation from a time ti shown in FIG. 19 or performs a datainput operation from a time tj shown in FIG. 20 as a data transferrequest source. The utilization of the channel identificationinformation ID outputted from a bus controller 5 is the same as the caseshown in FIG. 8. Thus, the data transfer can be directly processedwithout asserting an external data bus use request (without noting thestate of use of an external data bus).

[0116] According to the second handshake protocol transfer operation,the external I/O 65 can start the data transfer of the DMAC 8 withoutacquiring the bus right where it is unnecessary to change the datatransfer control conditions initially set by the command for the firstnormal data transfer operation.

[0117]FIG. 21 is a diagram for describing a direct data transferoperation in which the transfer of data from an external I/O to a memoryis shown by way of example. FIG. 22 shows a timing chart concerning thetransfer of data from the external I/O to the memory during the directdata transfer operation. FIG. 23 illustrates a timing chart concerningthe transfer of data from the memory to the external I/O during thedirect data transfer operation.

[0118] The direct data transfer operation is an operation for settingthe data transfer control information by the CPU 3 and thereafterdemanding the data transfer from the external I/O 65, thereby performingDMA transfer without having to use the data bus 60. Each data transferchannel selected in this operation is fixedly determined in advance.

[0119] Described more specifically, a DDT controller 102 is allowed toassert a bus right request signal DBREQ and a data transfer requestsignal TR simultaneously. As a result, the DDT controller 102 recognizesthat a data transfer request using a data transfer channel 2 fixedlydetermined in advance has been made and requests a DMA controller 801 tostart data transfer through the use of a transfer request signalDDTREQ2. A DMAC 8 starts data transfer using the data transfer controlinformation already set to the data transfer channel 2 as it is. Thus, adata strobe signal TDACK is outputted together with each address signal.In synchronism with it, the external I/O 65 performs a data outputoperation from a time ti shown in FIG. 22 or performs a data inputoperation from a time tj shown in FIG. 23 as a data transfer requestsource.

[0120]FIG. 24 is a diagram for describing a data transfer interruptoperation. FIG. 25 shows a timing chart of the data transfer interruptoperation.

[0121] The data transfer interrupt operation is carried out as follows:A DDT controller 102 detects a state in which a data transfer setcommand supplied from the external I/O 65 is placed in a specific state,e.g., ID1, ID0= “0, 0”, MD1, MD0≠“0, 0” and SZ2, SZ1, SZ0=“1, 1, 1” tothereby force-complete a data transfer control operation. Here, a buscontroller 5 gives the highest priority to a bus right request signalDBREQ outputted from the external I/O 65. When the bus right requestsignal DBREQ is outputted from the external I/O 65 even during a DMAdata transfer operation, the bus controller 5 stops a bus access whichis being executed at that time and releases a bus right to the externalI/O 65.

[0122] According to the data transfer interrupt operation, when theexternal I/O 65 desires to demand a data transfer, it can stop the datatransfer operation of the already-activated DMAC 8 and make a requestfor the data transfer with the highest priority.

[0123] While the invention made by the present inventors, has beendescribed specifically based on various embodiments, the presentinvention is not limited to those embodiments. It is needless to saythat various changes can be made thereto within a scope not departingfrom the subject of the invention as set forth therein.

[0124] For example, DMA data transfer, in which an external I/O is setas a data transfer source, is not necessarily limited to the transfer ofdata between the external I/O and a memory. This data transfer may be adata transfer between the external I/O and another input/output device.Further, circuit modules incorporated in a microcomputer and deviceswhich constitute a data processing system are not limited to thoseemployed in the above-described embodiments and may be suitably changed.Moreover, a DMAC is not limited to a configuration using a data bufferprovided inside a bus controller 5. The DMAC itself may be set to aconfiguration having a dedicated data buffer.

[0125] Further, the external I/O 65 may be comprised of onesemiconductor chip or a combination of a plurality of semiconductorchips. Moreover, the present I/O may be provided on the samesemiconductor chip as that for a microcomputer.

[0126] Although the data bus and the external I/O are connected to oneanother by two buses in FIG. 3, they may be of course coupled to eachother by one bus. Further, if a plurality of external I/O's are preparedand transfer information (transfer destination or transfer sourceaddress data, transfer channels, etc.) inherent in the external I/O isset (stored in a command ROM), then data transfer corresponding to achanged external I/O is initially set by simply changing the externalI/O, whereby the system is easily changed. In this case, the respectiveexternal I/O may of course be configured so as to have functionsdifferent from each other or the same function.

[0127] Further, only one external I/O is connected to the bus in theaforementioned embodiments. However, a plurality of external I/O's maybe connected to the bus. In this case, it is desirable that bus rightrequests do not overlap each other or are given a priority.

[0128] Effects obtained by a typical one of the features disclosed inthe present application will be briefly described as follows.

[0129] That is, an external input/output device can output a datatransfer set command together with a data transfer request withoutinvolving a CPU upon execution of data transfer and set data transfercontrol information to direct memory access control means. Therefore,when the input/output device used as a data transfer request sourcedesires to perform the data transfer, the input/output device canperform data transfer processing with its timing without recognizing ornoting the state of processing by a CPU and hence data transfer with theinput/output device as a principal base can be performed.

[0130] Since, at this time, the CPU is not required for the initialsetting of the data transfer control information, no load is imposed tothe CPU and the CPU can be directed to other processes during that time,whereby the data processing performance of a microcomputer and the dataprocessing performance of the data processing system as a whole can beimproved.

What is claimed is:
 1. A data processing system, comprising: amicrocomputer; a memory; an input/output device; and at least one bus towhich said microcomputer, said memory and said input/output device areconnected; said microcomputer including, a central processing unit;direct memory access control means having a plurality of data transferchannels, for performing data transfer control based on data transfercontrol information supplied from said central processing unit or theoutside through said bus; and a bus state controller for arbitratingcompetition between bus right requests supplied from said centralprocessing unit, said direct memory access control means and saidinput/output device and controlling a bus cycle for said bus, saidinput/output device acquiring a bus right to perform a data transferrequest to said direct memory access control means and outputting a datatransfer set command for controlling the operation of said direct memoryaccess control means to said bus, and performing the operation ofinputting data to or outputting data from said bus in synchronism with aresponse issued from said microcomputer as a data transfer source forthe control of data transfer by said direct memory access control means.2. The data processing system according to claim 1 , wherein said datatransfer set command includes information for respectively designating atransfer data size, data transfer channels used for data transfer,transfer addresses, and the number of transfers.
 3. A data processingsystem, comprising: a microcomputer; a memory; an input/output device;and at least one bus to which said microcomputer, said memory and saidinput/output device are connected, said microcomputer including, acentral processing unit; direct memory access control means having aplurality of data transfer channels, for performing data transfercontrol based on data transfer control information supplied from saidcentral processing unit or the outside through said bus; and a bus statecontroller for arbitrating competition between bus right requests issuedfrom said central processing unit, said direct memory access controlmeans and said input/output device and controlling a bus cycle for saidbus, said input/output device acquiring a bus right to perform a datatransfer request to said direct memory access control means andoutputting a data transfer set command for controlling the operation ofsaid direct memory access control means to said bus, and performing theoperation of inputting data to or outputting data from said bus insynchronism with a response issued from said microcomputer as a datatransfer source for the control of data transfer by said direct memoryaccess control means, and said direct memory access control means havinga first operation for performing data transfer control in accordancewith the data transfer control information set by said data transfer setcommand.
 4. The data processing system according to claim 3 , whereinsaid direct memory access control means has a second operation fordetecting, after said first operation, that the data transfer setcommand supplied together with the data transfer request from saidinput/output device is placed in a specific first state, to therebyperform data transfer control according to the set data transfer controlinformation, using the same data transfer channel as that for said firstoperation.
 5. The data processing system according to claim 3 , whereinsaid direct memory access control means has a third operation forreceiving a data transfer request from said input/output device withoutthe delivery of a data transfer set command after said first operationto thereby perform data transfer control according to the set datatransfer control information, using the same data transfer channel asthat for the immediately preceding data transfer operation.
 6. The dataprocessing system according to claim 3 , wherein said direct memoryaccess control means has a fourth operation for receiving the datatransfer request from said input/output device with the data transferset command after data transfer control information is set by saidcentral processing unit to thereby perform data transfer controlaccording to the data transfer control information set by said centralprocessing unit, using a data transfer channel specified by the datatransfer set command.
 7. The data processing system according to claim 6, wherein said direct memory access control means has a fifth operationfor receiving a data transfer request from said input/output devicewithout the delivery of the data transfer set command after datatransfer control information is set by said central processing unit,thereby performing data transfer control according to the set datatransfer control information, using the same data transfer channel asthat for the immediately preceding data transfer operation.
 8. The dataprocessing system according to claim 3 , wherein said direct memoryaccess control means detects that the data transfer set command suppliedfrom said input/output device is placed in a specific second state, tothereby forced-complete a data transfer control operation.
 9. The dataprocessing system according to claim 4 , wherein said direct memoryaccess control means detects that the data transfer set command suppliedfrom said input/output device is placed in a specific second state, tothereby forced-complete a data transfer control operation.
 10. The dataprocessing system according to claim 5 , wherein said direct memoryaccess control means detects that the data transfer set command suppliedfrom said input/output device is placed in a specific second state, tothereby forced-complete a data transfer control operation.
 11. The dataprocessing system according to claim 6 , wherein said direct memoryaccess control means detects that the data transfer set command suppliedfrom said input/output device is placed in a specific second state, tothereby forced-complete a data transfer control operation.
 12. The dataprocessing system according to claim 7 , wherein said direct memoryaccess control means detects that the data transfer set command suppliedfrom said input/output device is placed in a specific second state, tothereby forced-complete a data transfer control operation.
 13. Amicrocomputer, comprising: a central processing unit; direct memoryaccess control means having a plurality of data transfer channels, forperforming data transfer control based on data transfer controlinformation supplied from said central processing unit or the outside;and a bus state controller for arbitrating competition between bus rightrequests supplied from said central processing unit, said direct memoryaccess control means and the outside and controlling a bus cycle for theoutside, said direct memory access control means having a firstoperation for, when a data transfer request is given from the outsidewith a data transfer set command for controlling the operation of saiddirect memory access control means in a state in which said bus statecontroller has released a bus right to the outside, performing datatransfer control in accordance with the data transfer controlinformation set by the data transfer set command.
 14. The microcomputeraccording to claim 13 , wherein said direct memory access control meanshas a second operation for detecting after said first operation that adata transfer set command supplied together with a data transfer requestfrom the outside is placed in a specific first state, to thereby performdata transfer control according to the set data transfer controlinformation, using the same data transfer channel as that for said firstoperation, and a third operation for receiving a data transfer requestfrom the outside without the delivery of a data transfer set commandafter said first operation to thereby perform data transfer controlaccording to the set data transfer control information, using the samedata transfer channel as that for the immediately preceding datatransfer operation.
 15. The microcomputer according to claim 13 ,wherein said direct memory access control means has a fourth operationfor receiving a data transfer request from the outside with a datatransfer set command after the data transfer control information is setby said central processing unit, to thereby perform data transfercontrol according to the data transfer control information set by saidcentral processing unit, using a data transfer channel specified by thedata transfer set command, and a fifth operation for receiving a datatransfer request from said input/output device without the delivery of adata transfer set command after data transfer control information is setby said central processing unit, thereby performing data transfercontrol according to the set data transfer control information, usingthe same data transfer channel as that for the immediately precedingdata transfer operation.
 16. A microcomputer, comprising: a centralprocessing unit; a direct memory access controller having a register towhich control information used upon a data transfer operation is set,said direct memory access controller executing the data transferoperation in accordance with the control information set to saidregister; a bus connected to said central processing unit, said directmemory access controller and the outside of said microcomputer; a buscontroller connected to said central processing unit so as to receive ause request to said bus from the outside of said microcomputer and a userequest to said bus from said central processing unit and therebyarbitrate between the use requests to said bus; and a control circuitsetting control information supplied to said bus to said register ofsaid direct memory access controller when said bus controlleracknowledges a bus use request from the outside.
 17. The microcomputeraccording to claim 16 , wherein the control information set to saidregister includes transfer source address information indicative of atransfer source upon the data transfer operation or transfer destinationaddress information indicative of a transfer destination upon the datatransfer operation.
 18. The microcomputer according to claim 17 ,wherein said control circuit sets the control information supplied tosaid bus to said register in response to a transfer request to saiddirect memory access controller.
 19. The microcomputer according toclaim 18 , wherein said direct memory access controller has a pluralityof data transfer channels and said register has a plurality of registersrespectively corresponding to said plurality of data transfer channels,said registers being assigned to mutually different addresses by saidcentral processing unit, whose each address is specified to thereby setcontrol information to the corresponding register assigned to thespecified address by said central processing unit.
 20. The microcomputeraccording to claim 19 , wherein the control information supplied to saidbus includes information for specifying one of said plurality of datatransfer channels, and the transfer source address information or thetransfer destination address information is set to the registercorresponding to the data transfer channel specified by the specifyinginformation.
 21. A device connected to a bus and which functions as adata transfer source or a data transfer destination upon a data transferoperation, comprising: a processor implementing a predeterminedfunction; a controller outputting a use request to said bus andoutputting a data transfer request in response to approval for the userequest; and an output unit outputting control information used upon thedata transfer operation in synchronism with the output of the datatransfer request.
 22. The device according to claim 21 , wherein saidcontrol information includes address information for a transferdestination to transfer data upon the data transfer operation or addressinformation indicative of an address for a transfer source in which eachdata to be transferred is stored.
 23. The device according to claim 22 ,wherein said processor, said controller and said output unit are formedon one semiconductor chip.
 24. The device according to claim 22 ,wherein said device is comprised of a plurality of semiconductor chips.25. A data processing apparatus, comprising: a microcomputer; a buscoupled to said microcomputer; and a device coupled to said bus; saidmicrocomputer including, a central processing unit coupled to said bus;a direct memory access controller coupled to said bus and having atleast one register to which control information used upon a datatransfer operation is set, said direct memory access controllerexecuting the data transfer operation in accordance with the controlinformation set to said register; a bus controller connected to saidcentral processing unit so as to receive a use request to said bus fromthe outside of said microcomputer and a use request to said bus fromsaid central processing unit and thereby arbitrate between the userequests to said bus; and a control circuit setting control informationsupplied to said bus to said register of said direct memory accesscontroller when said bus controller acknowledges a bus use request fromthe outside, and said device including, a processor implementing apredetermined function; a controller outputting a use request related tosaid bus and outputting a data transfer request in response to approvalfor the use request; and an output unit outputting the controlinformation in synchronism with the output of the data transfer request.26. The data processing apparatus according to claim 25 , wherein saidcontrol information includes address information for a transferdestination to transfer data upon the data transfer operation or addressinformation indicative of an address for a transfer source in which eachdata to be transferred is stored.
 27. The data processing apparatusaccording to claim 26 , wherein said control circuit sets the controlinformation supplied to said bus to said register in response to a datatransfer request to said direct memory access controller.